I have always wondered why there was never a big market[1] for "cheap PCI/PCI-X/PCI-e card you can stick a boatload of your old/surplus/n-generation old simms/dimms on and use as swap/slow memory/ram disk/etc". It's rare you can populate a motherboard with a full address space full of 'new' memory, and you can teach kernels to prefer some memory to others because of speed[2], so it seems like a no-brainer.
I seem to remember the market for doing similar with flash got neutered over patent issues, but I can't recall the details. And flash cache did end up being a market, at least for bigger players. Maybe something similar happened here, or maybe it just hit a niche I cared about at the time?
[1] I know there were a handful of products in this space, but my impression is they never really took off. I could be wrong.
[2] Definitely can in NetBSD; I've done it for archs like VMEbus where it's common to have a small, fast on board memory and much slower, often larger memory out on the bus. I assume this sort of thing is enabled in Linux by the work to support NUMA, but I've never looked into it.
There was never a big market for it because new memory was not prohibitively expensive in comparison to the cost and risk of using old memory in a new server. That is not the case now, so people are looking at the idea again.
From a quick skim, you could think of this as roughly equivalent to shoving a large amount of DDR4 on a PCIe card and using it as a swap space. It's more sophisticated (see CXL protocol), but that gives you an idea of the tradeoffs. It seems there is some OS-level support for moving hot/cold pages between the main fast DRAM and the expansion higher latency DRAM.
It's a very valid point that DRAM has a fairly long lifetime and contains significant embedded carbon emissions, as well as the current availability crisis of new DRAM.
"Second, memory dominates the carbon footprint of
the fleet [8], accounting for 69% of CO2 emissions and posing
a significant sustainability challenge [4]. DRAM dominates
datacenter embodied CO2 largely because it is ubiquitous
and deployed in large quantities across essentially all servers.
Based on our internal fleet data, and aligned with studies
from other hyperscalers such as Microsoft [33], memory is
one of the largest single embodied-emissions contributors"
[8] U. Gupta, M. Elgamal, G. Hills, G.-Y. Wei, H.-H. S. Lee, D. Brooks,
and C.-J. Wu, “ACT: Designing Sustainable Computer Systems with an
Architectural Carbon Modeling Tool,” in Proceedings of the 49th Annual
International Symposium on Computer Architecture (ISCA’22), 2022.
[4] D. Azevedo, M. Patterson, J. Pouchet, and R. Tipley, “Carbon usage
effectiveness (cue): A green grid data center sustainability metric,” White
paper, vol. 32, 2010.
[33] J. Wang, D. S. Berger, F. Kazhamiaka, C. Irvene, C. Zhang, E. Choukse,
K. Frost, R. Fonseca, B. Warrier, C. Bansal, J. Stern, R. Bianchini,
and A. Sriraman, “Designing Cloud Servers for Lower Carbon,” in
Proceedings of the 51st Annual International Symposium on Computer
Architecture, ser. ISCA ’24, 2025, p. 452–470.
Not a reference, but I found https://www.interface-eu.org/publications/semiconductor-emis... which goes into great detail on the subject. I hadn't realized there were significant emissions of fluorinated gases directly from the fabs, which is mildly alarming. Although it looks like there has been a crackdown on this either politically or through ESG policies.
CXL Vistara reminds me a bit of the AST Rampage 286 memory expansion ISA card I had in my 286 back in the day, as a kid. Things go in circles, I guess.
Adding the RAM to the system this way isn’t exactly like expanding the main system RAM. The RAM is connected over a PCIe type link so it doesn’t behave like the primary RAM.
It’s better for server farms where engineers can customize and tune for an architecture like this.
There have been some cards that use RAM as a storage device. They were never popular because having to set it up as a disk had very limited use cases.
Necessity is the mother of invention, after all. (One of the oldest abstract concepts in intellectual thought, I suspect.)
There is a tight resource starvation/motivation loop — the demand put on RAM and SSD and GPUs by the largest frontier models is a direct motivation to make smaller LLMs. Like an evolutionary pressure making animals smaller and more food-efficient.
These smaller models, once successful, are still likely to consume more RAM and SSD and GPUs than any other application short of high quality video processing itself (the smaller LLMs and higher end video processing seem to have about the same needs). But the resources would distribute through the market more traditionally, leading to less insane cycles.
So it seems to me that the way out of the RAM/SSD price cycle crisis that manufacturers are in — where the price fluctuates between high and low due to supply constraints and then oversupply from new production capacity - is for them to fund research into smaller LLMs. They'll still sell essentially the same amount of product. Maybe more.
With regards to RAM price I never understood the following: A 16GB RAM stick has 16*8=128 billion bits, with 1 transistor per bit, thats still 128B, yet its supposed to cost like $60 before the price hikes? In contrast, a 5090 GPU was $2000 (true it has RAM, but you're paying for the GPU ASIC really, I guess the rest of the GPU was less than $500), it had 93B transistors.
GPU transistors are smaller due to the more advanced process node (cost per transistor metrics aren't really clear, if they improve on advanced node or not, but I'd say they get cheaper as they get smaller, as technology costs are amortized).
I'm sure both RAM and logic use a process that is quite similar in both inputs and manufacturing steps. So while RAM is a commodity product, this insane price difference didn't make any sense.
So I guess when those fundamental inputs become a constraint, it would make sense for $/transistor move closer for both, which is a massive hike for RAM.
Chip fabrication processes are not fungible: GPUs and CPUs might be made on roughly the same process, but DRAM is not (flash is a different process again, as is power electronics, analog electronics, MEMS, etc. And even within those broader categories there are different variations). While there are some overlaps in machines and techniques, a fab set up for one cannot generally switch to the other, and the economics of each process can also be drastically different.
You're not the first person to say so (and I don't mean to dispute it), but I have never been able to find a clear answer for /why/ those processes are incompatible.
Is it built in different silicon, is it physical steps that's incompatible (ie its actually incompatible), is it different physical preparations that needs to be made (making it economically infeasible to combine)
I cannot help but wonder, even if the answer doesn't change anything in my life.
Medium ELI5 answer: each company and to a great extent each individual fab has a slightly different recipe, which is known as a "process node". This defines all the fabrication steps, every individual layer and its chemical/physical processing.
This in turn affects the electrical properties: parasitic resistance/capacitance, gate dielectric properties and so on. The dielectric in particular is critically different between DRAM and regular CMOS, because DRAM needs to minimise leakage (as that determines how long the memory lasts between refresh cycles).
Regular factories will retool somewhat between jobs. Because it is quite difficult to finetune a silicon process node, it is more common that a fab will set up for a particular node and then switch to "do not touch or change anything under any circumstances", as doing so may wreck yields.
("different substrate entirely" does exist: that's GaN, for power transistors in phone chargers, and SiC, for even higher power transistors.)
At a very abstract level, when you're manufacturing DRAM you need to manufacture a lot of circuit elements that have HIGH capacitance, since a DRAM cell is basically a capacitor and the higher its capacitance the less frequently it needs to be refreshed.
On the other hand, when manufacturing logic (CPU/GPU/ASIC) you want to minimize the capacitance of almost all circuit elements, since capacitance introduces delay and switching energy cost.
Nearly everything about the manufacturing processes for DRAM and logic is optimized around this fundamentally incompatible figure of merit.
I worked on the development of Intel's eDRAM process, which was used to integrate DRAM into the CPU/GPU die for Iris Pro embedded graphics from 2013-23. https://ieeexplore.ieee.org/document/6576667/
The physical structure is completely different. Just compare DRAM ([0]) with compute ([1]). As a result, the production process is completely different.
If you want to know more, the Asianometry youtube channel has some fairly good deep dives, such as [2] going through a decent bunch of the 45nm production process, or [3] doing the same for (early) DRAM.
from my basic understanding, memory is much easier to produce then logic chips like GPUs and CPUs, they don't need that many photolithographic layers. while it could be possible to produce memory in fabs for CPUs (though not really desirable in regard to costs) the other way round is more difficult
> but I have never been able to find a clear answer for /why/ those processes are incompatible.
You can't find an explanation why they're different for the same reason you can't find an explanation why writing poetry and riding a unicycle isn't the same process.
Or, you could look at your peer answers where people very much do provide a non hand-wave answers. Chip fabrication isn't undergrad philosophy; there are well understood reasons for why things are done if you care to find and understand them. And there are stakes in the millions or billions of US$ for getting them wrong.
RAM is literally copy-paste of the same circuit over and over, you're trying to compare cost to produce million AK-47 with 1 carrier
and cost per transistor stopped decreasing at ~20-30nm, now small nodes are targetting energy efficiency (and thus performance, since heat is the main limiter)
On top of everything said, 5090 die size is 10x than typical DDR5 die size. One RAM module is 8-16 dies, so you do get more silicon in the end, but larger dies are extremely expensive to produce due to sharply decreasing yields.
The thing that defines performance of DRAM is AFAIK the capacitor of the bit cells and not the transistor driving it. And also AFAIK the process to create those capacitors is quite unique to DRAM, so you can't just go and use a "logic" process unchanged and produce DRAMs.
newer process node are smaller but very expensive compared to mature ones, each wafer from TSMC latest process is costly and with lower yield due to GPU large die size (+700mm2 compared to around 60mm2 per DRAM die)
Nobody voted for it, that's true. But since reality held closely to it for decades right up to the present, it's reasonable to believe that transistors get smaller and cheaper as time passes.
A GPU Transistor is a lot more complicated than a RAM transistor and the size of these are quite different too. Bleeding edge vs. a known process with know machines and written off machines.
Also you calculate in the machine cost and R&D.
RAM hiked because the demand spiked and these companies are now in power. Before apple and other companies told them the prices and had hardly any money for investment.
RAM is a commodity. It has much less moat to prevent competitions. When the rams flood the market that's when the bubble ends, until the next cycle arrives. Processors are much harder to design and commoditize.
> So while RAM is a commodity product, this insane price difference didn't make any sense.
Supply and demand coupled with the fact that a RAM fab can't (trivially) output compute chips, and vice versa, a compute fab can't output RAM. It's two completely different supply chains.
I seem to remember the market for doing similar with flash got neutered over patent issues, but I can't recall the details. And flash cache did end up being a market, at least for bigger players. Maybe something similar happened here, or maybe it just hit a niche I cared about at the time?
[1] I know there were a handful of products in this space, but my impression is they never really took off. I could be wrong. [2] Definitely can in NetBSD; I've done it for archs like VMEbus where it's common to have a small, fast on board memory and much slower, often larger memory out on the bus. I assume this sort of thing is enabled in Linux by the work to support NUMA, but I've never looked into it.
https://www.theregister.com/systems/2026/06/29/zuck-saves-me...
From a quick skim, you could think of this as roughly equivalent to shoving a large amount of DDR4 on a PCIe card and using it as a swap space. It's more sophisticated (see CXL protocol), but that gives you an idea of the tradeoffs. It seems there is some OS-level support for moving hot/cold pages between the main fast DRAM and the expansion higher latency DRAM.
It's a very valid point that DRAM has a fairly long lifetime and contains significant embedded carbon emissions, as well as the current availability crisis of new DRAM.
Hi - thanks for the insightful comment - could you please expand on the above?
Genuinely curious :)
"Second, memory dominates the carbon footprint of the fleet [8], accounting for 69% of CO2 emissions and posing a significant sustainability challenge [4]. DRAM dominates datacenter embodied CO2 largely because it is ubiquitous and deployed in large quantities across essentially all servers. Based on our internal fleet data, and aligned with studies from other hyperscalers such as Microsoft [33], memory is one of the largest single embodied-emissions contributors"
[8] U. Gupta, M. Elgamal, G. Hills, G.-Y. Wei, H.-H. S. Lee, D. Brooks, and C.-J. Wu, “ACT: Designing Sustainable Computer Systems with an Architectural Carbon Modeling Tool,” in Proceedings of the 49th Annual International Symposium on Computer Architecture (ISCA’22), 2022.
[4] D. Azevedo, M. Patterson, J. Pouchet, and R. Tipley, “Carbon usage effectiveness (cue): A green grid data center sustainability metric,” White paper, vol. 32, 2010.
[33] J. Wang, D. S. Berger, F. Kazhamiaka, C. Irvene, C. Zhang, E. Choukse, K. Frost, R. Fonseca, B. Warrier, C. Bansal, J. Stern, R. Bianchini, and A. Sriraman, “Designing Cloud Servers for Lower Carbon,” in Proceedings of the 51st Annual International Symposium on Computer Architecture, ser. ISCA ’24, 2025, p. 452–470.
Not a reference, but I found https://www.interface-eu.org/publications/semiconductor-emis... which goes into great detail on the subject. I hadn't realized there were significant emissions of fluorinated gases directly from the fabs, which is mildly alarming. Although it looks like there has been a crackdown on this either politically or through ESG policies.
Which seems to be the sister site of Register; https://www.blocksandfiles.com/architecture/2026/06/26/panmn...
"Our CXL solution achieves substantial gains for diverse workloads, including up to a 25% reduction in server count for disaggregated ML inference"
How does using worse RAM result in 25% reduction of server count for given workloads?
https://www.marvell.com/products/cxl.html
https://en.wikipedia.org/wiki/I-RAM
It’s better for server farms where engineers can customize and tune for an architecture like this.
There have been some cards that use RAM as a storage device. They were never popular because having to set it up as a disk had very limited use cases.
This yields for exciting ideas or workarounds that might result a post-crisis memory boom (hopefully) also for local machines.
1. Lowest, Apple is evaluating new Chinese manufacturer which means change of supply demand if indeed it has reasonable QA. (https://www.ft.com/content/f4ac5c92-03be-4499-b16a-017a7e9ee...)
2. Companies tries to workaround performance - suddenly single channel is 'ok' ? :) (https://www.gigabyte.com/press/news/2403)
Single channel RAM surely beats any disk-based swap.
There is a tight resource starvation/motivation loop — the demand put on RAM and SSD and GPUs by the largest frontier models is a direct motivation to make smaller LLMs. Like an evolutionary pressure making animals smaller and more food-efficient.
These smaller models, once successful, are still likely to consume more RAM and SSD and GPUs than any other application short of high quality video processing itself (the smaller LLMs and higher end video processing seem to have about the same needs). But the resources would distribute through the market more traditionally, leading to less insane cycles.
So it seems to me that the way out of the RAM/SSD price cycle crisis that manufacturers are in — where the price fluctuates between high and low due to supply constraints and then oversupply from new production capacity - is for them to fund research into smaller LLMs. They'll still sell essentially the same amount of product. Maybe more.
TIL there are 2x 2.5GbE PCI-E HAT adapters for Pi 5.
How to attach RAM to the new NVLink/UALink fiber buses?
GPU transistors are smaller due to the more advanced process node (cost per transistor metrics aren't really clear, if they improve on advanced node or not, but I'd say they get cheaper as they get smaller, as technology costs are amortized).
I'm sure both RAM and logic use a process that is quite similar in both inputs and manufacturing steps. So while RAM is a commodity product, this insane price difference didn't make any sense.
So I guess when those fundamental inputs become a constraint, it would make sense for $/transistor move closer for both, which is a massive hike for RAM.
Is it built in different silicon, is it physical steps that's incompatible (ie its actually incompatible), is it different physical preparations that needs to be made (making it economically infeasible to combine)
I cannot help but wonder, even if the answer doesn't change anything in my life.
This in turn affects the electrical properties: parasitic resistance/capacitance, gate dielectric properties and so on. The dielectric in particular is critically different between DRAM and regular CMOS, because DRAM needs to minimise leakage (as that determines how long the memory lasts between refresh cycles).
Regular factories will retool somewhat between jobs. Because it is quite difficult to finetune a silicon process node, it is more common that a fab will set up for a particular node and then switch to "do not touch or change anything under any circumstances", as doing so may wreck yields.
("different substrate entirely" does exist: that's GaN, for power transistors in phone chargers, and SiC, for even higher power transistors.)
At a very abstract level, when you're manufacturing DRAM you need to manufacture a lot of circuit elements that have HIGH capacitance, since a DRAM cell is basically a capacitor and the higher its capacitance the less frequently it needs to be refreshed.
On the other hand, when manufacturing logic (CPU/GPU/ASIC) you want to minimize the capacitance of almost all circuit elements, since capacitance introduces delay and switching energy cost.
Nearly everything about the manufacturing processes for DRAM and logic is optimized around this fundamentally incompatible figure of merit.
I worked on the development of Intel's eDRAM process, which was used to integrate DRAM into the CPU/GPU die for Iris Pro embedded graphics from 2013-23. https://ieeexplore.ieee.org/document/6576667/
A Reddit user explains a bit here.
If you want to know more, the Asianometry youtube channel has some fairly good deep dives, such as [2] going through a decent bunch of the 45nm production process, or [3] doing the same for (early) DRAM.
[0]: https://www.youtube.com/watch?v=Bln-v9LmZ3E
[1]: https://i1.wp.com/semiengineering.com/wp-content/uploads/201...
[2]: https://www.youtube.com/watch?v=zUgy29h0alM
[3]: https://www.youtube.com/watch?v=uPualBNf1nM
You can't find an explanation why they're different for the same reason you can't find an explanation why writing poetry and riding a unicycle isn't the same process.
and cost per transistor stopped decreasing at ~20-30nm, now small nodes are targetting energy efficiency (and thus performance, since heat is the main limiter)
Also you calculate in the machine cost and R&D.
RAM hiked because the demand spiked and these companies are now in power. Before apple and other companies told them the prices and had hardly any money for investment.
Supply and demand coupled with the fact that a RAM fab can't (trivially) output compute chips, and vice versa, a compute fab can't output RAM. It's two completely different supply chains.